1. Field of the Invention
The invention relates to a semiconductor device and a substrate used in thereof and, in particular, to a semiconductor device and a substrate used in thereof having an electrostatic discharge protection function.
2. Related Art
Due to the high integrity and the needs of the consuming market, the sizes of semiconductor devices have become more compact. Therefore, many semiconductor package technologies have been developed, such as PGA (Pin Grid Array), BGA (Ball Grid Array), and wafer level packaging.
Among the aforementioned package technologies, the substrate 11 of a BGA semiconductor device 1 (as shown in FIG. 1) is used more efficiently to have more bumps 13. The bumps 13 electrically connect to the pads of the die chip 12 via the trace lines and pads on the substrate 11. Since the number of the bumps is larger, the die chip 12 can transmits larger amount of signals via the bumps 13.
Please refer to FIG. 2, the above-mentioned substrate 11 includes a first wiring layer 21, a ground interconnection-wiring layer 22, a power interconnection-wiring layer 23, and a second wiring layer 24. These four layers are stacked in sequence to form the substrate 11. The top surface of the first wiring layer 21 is provided with a plurality of first pads 211 for electrically connecting to the pads of the die chip 12. Furthermore, a plurality of first trace lines 212 are formed in the first wiring layer 21. One end of each of the first trace lines 212 connects to a corresponding first pads 211.
The ground interconnection-wiring layer 22 and the power interconnection-wiring layer 23 connect to specific pads in the first wiring layer 21 (a ground ring) and specific pads of the second wiring layer 24 (a power ring), respectively, to provide a ground voltage level and a power voltage level to the die chip 12 from an external circuit.
The bottom surface of the second wiring layer 24 is provided with a plurality of second pads 241, each of which is formed with a bump 13. Moreover, a plurality of second trace lines 242 are formed in the second wiring layer 24, one end of each of the second trace lines 242 connects to a corresponding second pads 241. Another end of each of the first trace lines 212 connects another end of each of the second trace lines 242 via a via hole (not shown in the drawing). The pads of the die chip 12 communicate with external circuits through the first pads 211, the first trace lines 212, the via holes, the second trace lines 242, the second pads 241, and the bumps 13.
From the above, since the number of second pads 241 provided by the substrate 11 to connect with the bumps 13 usually exceeds the number of the pads of the die chip 12, some of the bumps 13 are not electrically connected with pads of the die chip 12. These bumps 13 are called NC Balls. More specifically, the second pads connected with the NC Balls do not connect with the second trace lines, thus the NC Balls do not electrically connected with the pads of the die chip 12. The reason to reserve these NC Balls is to provide input/output terminals required when the function of the semiconductor device (such as the BGA semiconductor device 1 mentioned above) is improved. However, when the above-mentioned BGA semiconductor device 1 is under operation, the NC Balls are in a floating status. Under this situation, if an ESD (electrostatic discharge) test is performed to these NC Balls, the electrostatic charges may move into the die chip to damage other functional pins. If this happens, the functions of the BGA semiconductor device will become abnormal.
Therefore, how to provide a semiconductor device with a superior ESD protection capability has become an important issue to be solved.